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- Grid
Driving 64pF Capacitance at 4GHz Clock
7 May 2006
- Bitline
Phase III Submitted Report (PDF, 3 pages) | [Word]
22 Apr 2006
- Decoder Phase
II Submitted Report (PDF, 3 pages) | [Word]
3 Apr 2006
- Decoder
Phase II Detailed Report (PDF, 62 pages) | [Word] | [Files]
3 Apr 2006
- Decoder Phase II
Cadence Layout Report (PDF, 67 pages) | [Word]
3 Apr 2006
- Decoder Phase II
Dynamic Logic Report (PDF, 16 pages) | [Word]
3 Apr 2006
- SRAM
Design Phase I Cadence Layout (PDF, 34 pages) | [Word]
20 Mar 2006
- SRAM
Design Phase I Report (PDF, 16 pages) | [Word]
20 Mar 2006
- Lab 4 Circuit
Extraction from Cadence to hspice
13 Mar 2006
- HW6 Fanout
and NAND Chain Delay
28 Feb 2006
- HW5 Fanout,
Delay, and Capacitance (hspice)
24 Feb 2006
- Lab 3
CMOS Inverter and NAND Gates with Cadence Schematic Composer
17 Feb 2006
- Cadence
Schematic Composer Tutorial (PDF)
17 Feb 2006
- HW4 Find
tplh tphl tosc and beta (hspice)
17 Feb 2006
- HW3 Design Rule
Minimum for 0.25μm
Technology and Input/Output Capacitance (hspice)
9 Feb 2006
- Lab2
Cadence IC Layout Tool
4 Feb 2006
- Cadence
IC Layout Tutorial
4 Feb 2006
- HW2 Id vs Vds with
Vbs and Vds changes (hspice)
1 Feb 2006
- HW1/Lab1
Circuit Simulation with HSPICE, VTC of a MOSFET (hspice)
19 Jan 2006
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