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Verilog 16 August 2004 cd 61C 31 July 2004 VHDL Software List 31 July 2004
31 July 2004
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| 文章标题： [转帖]你选哪种仿真器：Modelsim、Verilog-xl、NC、VCS？ |
如果行为级仿真，我认为modelsim是最好的。在门级仿真，modelsim就很慢了。NC-Verilog是编译基础的Verilog仿真器，而Verilog-XL是基于解释的。速度上，NC-Verilog比Verilog-XL要快；特别是在门级仿真。在行为仿真时用modelsim或NC-Verilog，在门级仿真最好用用NC-Verilog。验证一个非常大的设计用Verilog-XL太慢。
VCS在RTL仿真是最快的。比NC大约要快10％。但是在门级仿真，VCS就比NC慢20％，而且有时产生一些错误。这时 NC是一个比较好的选择，而这时modelsim比VCS和NC都要慢，不过他提供很好的Verilog和VHDL的联合仿真。
To familiarize you with the basic syntax of Verilog.
By convention, Verilog files end in ".v". The command to compile such files is
iverilog -tvvp -Wall -o <output filename> <input files>
which is available only on nova.cs.berkeley.edu. Option -tvvp
indicates that the output is a complete program that simulates the design but
must be run using the command vvp. -Wall displays all
warnings. If you're interested, you can get more details on the options by
running man iverilog.
To run the output file, use the command
vvp
<output filename>
For this lab we shall write and test a circuit that performs the increment operation on a two-bit counter. The truth table for the operation is given below:
in1 in0 out1 out0
0 0 0 1
0 1 1 0
1 0 1 1
1 1 0 0
You are given 3 files, which include 2 testbenches testincrement.v and testincrement2.v, as well as increment.v which contains the incomplete module increment. These are located in ~cs61c/labs/lab4-2/.
Part 1: The boolean equation relating output out0 to inputs in1 and in0 is simply (out0 = not in0). What is the most concise boolean equation for the output out1 in terms of the inputs?
Part 2: The testbench testincrement.v is complete, but has 1 bug. Identity that bug (hint: it is on the line that instantiates our increment module).
Part 3: The module file increment.v is incomplete. Complete
it by filling in the equivalent of the boolean operations found in Checkoff 1
above. You must implement the boolean operations in structural Verilog,
that is, you can only use the modules and, or, not,
xor, nand, nor, xnor and buf. Show
your TA your working testbench and module by compiling and running them using
the following commands. Save the output to a file to show your TA when you get
checked off...
iverilog -tvvp -Wall -o testincrement testincrement.v increment.v
vvp testincrement
Part 4: testincrement2.v is a slightly modified version of testincrement.v. We instantiated a slightly different version of increment, but the basic functionality remains exactly the same: it still takes in two-bits, and returns those two-bits incremented by 1. Modify increment.v so that it works with testincrement2.v, and save the resulting file as increment2.v. Show your TA that you get the same results by compiling and running the modified files.
http://www.verilog.net/free.html
| Free Tools | |
| Vendor | Description |
| GPL Cver | free, open-source Verilog HDL simulator. Supports the full 1995 P1364 Verilog standard and some of the 2001 P1364 features, including all three PLI interfaces (tf_, acc_ and vpi_). System C. |
| Verilog2C++ | translates a C++ class of a Verilog design using a cycle-accurate representation of each nets and registers. Verilog2C++ is about 10 times faster than other commercial simulators, but has only simple functions. |
| Verilator | free Verilog simulator. Translates synthesizeable Verilog into C++ or System C. |
| VTracer | Verilog Testbench developer aid. Based on VCD dump file analysis performs design hierarchy extraction, trace comparison, stimuli generation, "and more." |
| VeriTCL | Verilog Scripting Environment, allows embedded TCL scripts in Verilog code. |
| ScriptSim | Seamless integration of Python, Perl, Tk and Verilog. |
| Verilog-Perl | Perl library is a building point for Verilog support. |
| Verilog++ | Verilog preprocessor allows arbitrary code including. |
| CRC RTL generation | On-line generation of synthesizable Verilog RTL for any CRC. |
| Another CRC RTL generation | On-line generation of synthesizable Verilog RTL for any CRC. |
| SynpatiCAD | Wellspring (maker of Veriwell) was purchased by SynaptiCAD. Free demo version still available. |
| VHDL to Verlog translator v1.0 | Free limited to a useful subset of VHDL, but it correctly translated a JPEG and Triple DES core sold at this site. |
| VBS | Free copy-lefted Verilog simulator called "vbs", written by Jimen Ching and Lay Hoon Tho. |
| Computer5 | Computer directory. Search for "Verilog". |
| OpenCores.org | Free IP cores. Not all cores are in Verilog, but the following are: Ethernet 10/100, UART16550, IDE, I2C, SDRAM/CS Memory Controller, USB 2.0, and VGA/LCD. |
| Chip Vault | Free VHDL/Verilog Chip Design organization tool. |
| Chip size estimator. | Free applet that estimates chip size. |
| VRTAGS | Free Verilog and Vera tags generator written in Perl by Jeff Koehler (mailto: J.Koehler@ieee.org). |
| SMASH mixed-signal simulator | Evaluation version, able to handle 50 digital nodes and 25 analog nodes. |
| Ver Structural Verilog Compiler | Portable, lightweight Verilog compiler without line limitations. Behavioral Verilog NOT supported. |
| Icarus Verilog | Verilog simulation and synthesis tool. Compiles Verilog into C++ or synthesizes into netlists. Under development. |
| Freeware Verilog/VHDL Project | Pages for people working on Free EDA tools, especially a Verilog-AMS simulator. Project is a work-in-progress. |
| Open Verification Library Initiative | An open source library containing Verilog modules used to specify properties of an HDL design to be verified, either in simulation or using formal or semi-formal methods. |
| Dinotrace | Free waveform viewer. |
| gtkWave | Free waveform viewer. |
| Win32 gtkWave | Free waveform viewer ported to Windows. |
| Genscript | Free version of Enscript printer-tool that knows Verilog (and other languages) |
| A2PS | Free tool to convert ASCII to PostScript, supports Verilog (and other languages). |
| PLI's by Chris Spear | including one to read and write files ("fileio"). from Verilog. |
| DC-PERL | Synopsys front-end, by Steve Golson. See also the paper at http://www.trilobyte.com/pdf/golson_snug97.pdf |
| vtags.pl | PERL script to build a tags file to be used by VI or Emacs. |
| vtags2.pl | Another tags file builder. |
| $plusarg | $value$plusargs PLI source for the proposed IEEE standard way to read plusargs . |
| FSMDesigner | Finite State Machine editor, Java-based. |
| Comit-TX | Verilog testbench extractor, creates a self-checking Verilog testbench. |
| Verilog Models | Linear<->A-Law converter, ADC, DAC and Serial EEPROM models. |
| Verilog Models | currently only resistor and Intel Flash memory models |
| VHD2VL | VHDL to Verilog translator. |
| V2HTML | Verilog to HTML converter |
| Verilog Preprocessor | VBPP Verilog preprocessors. |
| Verilog++ | a preprocessor for Verilog files that introduces two new constructs to Verilog: arbitrary code inclusion and a parametized module generation. |
| NEdit | Freely-distributable editor with syntax highlighting for Verilog and other languages |
| Structural Verilog Parser | C++ data structure and parser using lex/yacc. Only supports structural Verilog. |
| Verilog Parser | Originally from ftp.cray.com and submitted to comp.lang.verilog. |