The Term Project of UC Berkeley CS 150
Components and Design Techniques for Digital Systems

Signal

Width

Dir

Description

DIn

32

I

Packet data input bus

InValid

1

I

Indicates that DIn is valid on this cycle

InPacketValid

1

I

Indicates the end of a packet with a valid CRC

InPacketInvalid

1

I

Indicates the end of a packet with an invalid CRC

EthernetClock

1

I

25MHz Ethernet Clock

EthernetReset

1

I

EthernetClock synchronous reset

OutClock

1

I

12.288MHz Audio Clock

OutReset

1

I

OutClock synchronous reset

DOut

32

O

Audio data output bus

OutRequest

1

I

Request for a new audio word output

OutValid

1

O

Indicates that DOut is currently valid

datawords

P

There should be a datawords parameter, which will allow you to easily change the size of the packet decoded by this module

Signal

Width

Dir

Description

AP_SDATA_OUT

1

O

AC97 serial data output to the LM4549A

AP_BIT_CLOCK

1

I

A 12.288MHz gated clock.  You should use this for all audio circuitry.

AP_SDATA_IN

1

I

AC97 serial data input from the LM4549A

AP_SYNC

1

O

AC97 frame synchronization signal

AP_RESET_

1

O

Active low (Notice the _) reset for the LM4549A.  This will gate the AP_BIT_CLOCK

AP_PC_BEEP

1

O

PC beep output.  Tie to 1’b0.

Reset

1

I

System reset, synchronous to Clock, used with LocalResetGen

Clock

1

I

System 27MHz free running clock, used with LocalResetGen

PCM_DIn

32

I

32bit PCM data input.  Bits [31:16] is the left sample, bits [15:0] is the right sample.

PCM_InValid

1

I

Data valid input.  Indicates that PCM_DIn is valid.  Driven by Eth2Data.

PCM_InRequest

1

O

PCM_DIn request.  Causes a read from the Eth2Data FIFO.

PCM_DOut

32

O

PCM data output.  This would carry the data read from the microphone.  Unused this semester.

PCM_OutValid

1

O

Indicates that PCM_DOut has valid data.  Unused this semester.

CMD_AIn

7

I

The address of the AC97 register to write.

CMD_DIn

16

I

Data to write to the AC97 register indicated by CMD_AIn.

CMD_InValid

1

I

Indicates that CMD_DIn and CMD_AIn are valid in response to CMD_InRequest.

CMD_InRequest

1

O

Request by this controller for the next AC97 register to write.

AudioReset

1

O

Audio system reset.  Generated  by LocalResetGen.

AudioClock

1

O

12.288MHz audio system clock.  Another name for AP_BIT_CLOCK.

Signal

Width

Dir

Description

VolMaster

6

I

Volume control for all audio being played out the headphone jack on the CaLinx2 board.  Notice, there is a blue potentiometer which affects this also.

VolLineOut

6

I

Volume control for all audio being played out the RCA Line Out Jacks on the CaLinx2 board.

VolLineIn

6

I

Unused this semester.

VolWave

6

I

Volume control for all PCM data from the FPGA.

VolMic

6

I

Unused this semester

VolRecordGain

6

I

Unused this semester

RecordSource

3

I

Unused this semester

CMD_AOut

7

O

The address of the AC97 register to write.

CMD_DOut

16

O

Data to write to the AC97 register indicated by CMD_AOut.

CMD_OutValid

1

O

Indicates that CMD_DOut and CMD_AOut are valid in response to CMD_OutRequest.

CMD_OutRequest

1

I

Request from AC97Controller for the next AC97 register to write.

AudioReset

1

I

Audio system reset.

AudioClock

1

I

12.288MHz audio system clock.  Another name for AP_BIT_CLOCK.