20 Mar 2005
How do you use the log2(x) function in Const.v? I tried doing
`log2(somenumber) but it said it wasn't defined.
Frank Zhu
`ifdef MACROSAFE
localparam width = `log2(datawords);
`endif
Note the back quotes.
Make sure to have Const.v in your project.
Po-kai
06 Feb 2005
Comparator module Compare1 (A, B, Equal, Alarger, Blarger); input A, B; output Equal, Alarger, Blarger; assign Equal = (A & B) | (~A & ~B); assign Alarger = (A & ~B); assign Blarger = (~A & B); endmodule
// Make a 4-bit comparator from 4 1-bit comparators module Compare4(A4, B4, Equal, Alarger, Blarger); input [3:0] A4, B4; output Equal, Alarger, Blarger; wire e0, e1, e2, e3, Al0, Al1, Al2, Al3, B10, Bl1, Bl2, Bl3; Compare1 cp0(A4[0], B4[0], e0, Al0, Bl0); Compare1 cp1(A4[1], B4[1], e1, Al1, Bl1); Compare1 cp2(A4[2], B4[2], e2, Al2, Bl2); Compare1 cp3(A4[3], B4[3], e3, Al3, Bl3); assign Equal = (e0 & e1 & e2 & e3); assign Alarger = (Al3 | (Al2 & e3) | (Al1 & e3 & e2) | (Al0 & e3 & e2 & e1)); assign Blarger = (~Alarger & ~Equal); endmodule
Register module and_gate (out, in1, in2); input in1, in2; output out; reg out; always @(in1 or in2) begin out = in1 & in2; end endmodule
a. Blocking assignment looks like “=” and should be used in combinational logic. b. Non-blocking assignment looks like “<=” and should be used for sequential logic, namely anywhere you have an always @ (posedge Clock) c. Note that these kinds of assignment refer only to always blocks. The assign keyword always requires a simple “=”.
always @ (posedge Clock) implies a register.
Any reg assigned using Non-blocking assignment (<=) in
an always @ (posedge Clock) block will become a
register during synthesis.
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