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31 July 2004

Verilogger Tutorial
1.1 Add Files to the Project

VeriLogger Pro uses a project to store information about the simulation settings and the list of files to be simulated. First you will create a project and add the Verilog model files.

1. Run VeriLogger Pro and select the Project > New Project menu option to open the New Project Wizard dialog.
2. Type add4test.hpj into the Project Name edit box and press the Finish button to create a new project and project directory.
3. Right click the User Source Files folder in the Project window to open the context menu and choose the Add HDL File(s) to Source File Folder menu option. This opens the Add Files dialog.

4. Select the add4.v and add4test.v files located in the SynaptiCAD\Examples\TutorialFiles\VeriloggerBasicVerilogSimulation directory. To select multiple files at the same time, select the first file then hold down the <CTRL> key while using the mouse to select any additional files.
5. Press the Open button to add the files to the project. Both file names should be visible on the project tree. If you do not see both files then repeat instructions 3 and 4 to add the missing file to the project.

VeriLogger Pro ships with a built in editor that can be used to view and edit source code. The built in editor can be replaced with your favorite editor as described in Section 4.6: Using an External Editor of the BugHunter Pro and VeriLogger Pro User's Manual.
In the Project window:

1. Double click on the add4.v file to view the source code. Scan the source code and see how the modules model the schematic for the 4-bit adder. Close the editor window when you are finished.
2. Click the Editor menu. Notice the Save HDL File, Open HDL File, and Editor/Report Preferences menu options. You will probably be using these options the most.

1.2 Build the Tree and Use the Editor Window

In this section we will build the project tree and use the tree to view the internal modules. When files are first added to the project, you can see the file name but you cannot see a hierarchical view of the modules inside the files. To view the internal modules on the project tree you must first build or run a simulation. The build command compiles the Verilog files and builds the Verilog tree. It does not run a simulation. For large projects build lets you quickly construct the tree without having to wait for a simulation to run. To build a project:

1. Press the yellow Build button on the simulation button bar. This will populate the Stimulus and Results diagram and fill out the Simulated Module in the Project window.

One module, testbed, is placed in the Simulated Model folder and surrounded by brackets to indicate that it is the top-level module (the highest-level instantiated component). All sub-modules can be viewed by descending the top-level module's tree. When the tree is expanded it can display the signals, ports, and components contained in each module. Expand the tree by using the + buttons:

1. Press the + button to the left of <<<testbed>>> to expand the project tree. Explore the sub nodes using the + buttons until you open the components folder of A1.
2. Double click on the fa0 component. This will open an editor window scrolled to the instantiation of fa0 and there is a yellow arrow to the left of the editor screen indicating the correct line. This feature lets you very quickly view component code in a large design. Close the editor when you are done.

1.3 Simulate the Project

When we built the project in the last section, the names of the internal signals in the top-level module were automatically added to the Stimulus and Results timing diagram window. This feature allows you to quickly set up a project and start simulating and debugging without having to stop and specify a set of signals. For large projects you may want to turn off this feature by choosing the Project > Project Settings menu and un-checking the Grab top level signals check box. For small projects the automatic signal watches save a lot of time so we will leave it on for the tutorial. First, let's simulate with the default signals:

1. Click the green Run button on the simulation button bar. This causes a simulation to start and run until the end of the simulation time or until a breakpoint is reached. The Diagram window should contain purple waveforms.
2. Verify that the sum and c_out are correctly being computed as x + y + c_in.

1.4 Watch and View Internal Signals

With VeriLogger you can watch any combination of signals listed under the top-level module tree in the Simulated Model folder. To demonstrate this we will set watches on the sum outputs for the full adders sub-modules that make up the 4-bit adder:

1. In the Project window, expand the top-level module tree of the Simulated Model and find the fa0 component.
2. Right click on the sum port for fa0 to open a context menu and choose the Watch Connection menu option. This adds the testbed.A1.fa0.sum signal to the Diagram window.
3. Press the green Run button to run another simulation. Verify that the testbed.A1.fa0.sum signal is the 0 bit of the testbed.sum[3:0] signal.

Signals can be removed from the watch list by selecting the signal name in the Stimulus and Results diagram and pressing the delete key.
Next we will experiment with different ways to view waveforms in the Diagram window:

1. In the time line above the signals in the Diagram window, left click down and hold to show a marker that displays the value of each signal. Release the mouse button without dragging.
2. Left click and drag the marker about 50ns in the time line window. When you release the mouse button, the window will zoom to display the time range that the mouse was dragged over.
3. Right click in the time line to zoom out on the waveforms.
4. Press the Zoom Full button on the Diagram window to return the zoom level to the entire simulation range.

1.5 Save the Project, Waveforms and Source Code

Next we will learn to save the project, waveforms, and source code. The project saves the simulation options and the names of the files contained on the project tree. It does not save the source code or the watched signals. To save the project:

1. Choose the Project > Save Project menu option.

The watch signals and simulation results are saved in the correct stimulus and results file. By making the watched signals separate from the project file, VeriLogger lets you set up different sets of watched signals so that you do not have to watch your entire design each time you simulate. Also watching small sections of your design makes it easier to detect bugs in a particular section and speeds up simulation execution. In the evaluation version of VeriLogger you cannot save the waveforms, however in the full version you can save using the following menu command:

1. Select the File > Save Timing Diagram menu option to save the active timing diagram window.
2. In the Project window, right click Stimulus & Results to open the context menu. These functions allow you to change the current Stimulus and Results diagram.

Each time you simulate, every open editor is queried to determine if the source code needs to be saved before the simulation starts. If you need to save the code before you are ready to perform a simulation, use one of the following menu options:

1. The Editor > Save HDL File menu option to save the source code in the editor with the focus.
2. The Editor > Save All menu option to save the source code in all opened editors.

To re-open a VeriLogger Project, first open the project and then load the timing diagram files.

Part 2: Graphical Test Bench Generation

In this section you will draw and simulate a test bench using the timing diagram editor.

2.1 Remove TestBench Model and Clean Results Diagram

Now we will set up the project for this section by removing the test bench file and saving the project under a different name.

1. Select the Project > Save Project As menu option and save the project under the name of add4wave.hpj.
2. In the Project window User Source File Folder, right click add4test.v and select the Remove Selected File from the Folder from the context menu.
3. Delete all of the signals in the Stimulus and Results diagram by selecting the signal names and clicking the delete key.
4. Verify that only one file, add4.v, is listed on the project tree, and that the Diagram window is empty.

2.2 Build the Project and Examine the Black Signals

In the previous section, all the signals were purple to indicate that they were simulated signals that were generated by the Verilog code. In this section we have deleted the testbed module and the new top level module has input port signals that are not being driven by any other module in the project. To verify this:

1. Verify that the Simulate > Simulate Diagram With Project menu option is checked. This option lets the simulator compile both the drawn waveforms and the Verilog source code files together.
2. Press the Extract the MUT ports into Diagram on the simulator button bar.
3. Notice that the Diagram window now has two purple signals and three black signals. The purple signals are "simulated" signals whose values will be determined during the next simulation (once they are simulated they will turn purple). The black signals are input signals that need to be defined before a non-trivial simulation can take place.

4. Use the Project tree to verify that the black signals are input ports of the <FourBitAdder> module.

2.3 Use the Debug Run and Simulation Mode

VeriLogger has two simulation modes: Auto Run and Debug Run. The simulation mode is displayed on the left most button on the simulation button bar. In the Debug Run mode, simulations are started only when the user presses the Run or Single Step buttons (similar to a standard Verilog simulator). In Auto Run mode the simulator will automatically run a simulation each time a waveform is edited in the Waveform window. This mode makes it easy to quickly test small modules and perform bottom-up testing. While drawing the original test bench we will set the simulator to Debug Run mode:

1. Press the simulation mode button to toggle the display to Debug Run.

2.4 How to Draw Waveforms

If you are already familiar with SynaptiCAD's timing diagram editing environment, skip ahead to Section 2.6 where you will draw stimulus vectors and use the Virtual State edit box to define the values for the x and y busses.
If this is your first time using a SynaptiCAD timing diagram editor then we will first draw several random waveforms to familiarize you with the drawing environment.

1. Notice the buttons with the waveforms drawn on them. These are the state buttons. The active button is colored red and indicates the state of the next segment drawn. In this case, the HIGH state button is probably active.

2. Move the mouse cursor to inside the drawing window at the same level as the signal name c_in, and at about 40ns.
3. Left click to draw a waveform segment from 0ns to the cursor. Notice that a HIGH signal was created.
4. A different state button is now activated. The state buttons automatically toggle between the two most recently activated states. The small red T above the state name denotes the toggle state.
5. Move the cursor to about 80ns on the same signal and left click. Now a LOW segment is drawn from the end of the HIGH signal to the location of the cursor.

6. Left click on the VAL button to activate the valid state button and draw another waveform segment.
7. Draw more segments, using all the states except the HEX button. We will use this button later to define the state values for the multi-bit signals. For now, experiment with the graphical states on each of the black signals (the purple signals are outputs of the simulation and cannot be drawn on).

Your drawing should be a mess, or at least look nothing like Figure 2 located in Section 2.6.

2.5 How to Edit Waveforms

There are four main editing techniques used to modify existing signals (Note: these techniques will not work on clocks and simulated signals). The most commonly used technique is the dragging of signal transitions to adjust their location. The other three techniques all act on signal segments (the waveforms between two consecutive signal transitions). The segment waveform can be changed, deleted, or a new segment can be inserted within another segment. Use each of the following techniques:

1. Move a signal transition: Left click and hold on a signal transition. A green bar will appear that follows the mouse cursor. Release the mouse button when the green bar is at the desired location.
2. Change the state of a segment: A segment is the waveform between two consecutive signal transitions. Left click on the segment to select it (a selected segment has a highlighted box drawn around it). Then left click on the state button of the new state desired.

3. Delete a segment: Select a segment, then press the <delete> key.
4. Insert a segment: Inside a large segment, left click down and drag to the right, then release. A new segment will be added in the middle of the original segment. For this operation to work, the original segment must be wide enough to be selected.

More waveform generation techniques are covered in the Timing Diagram Editor - Chapter 1: Signals and Waveforms on-line help.

31 July 2004

VeriLogger - an affordable and power Verilog simulator

Verilog Simulator with Graphical Test Vector Generation

VeriLogger Pro, by SynaptiCAD is a complete design and verification environment for ASIC and FPGA designers. It contains a new type of Verilog simulation environment that combines all the features of a traditional Verilog simulator with the most powerful graphical test vector generator on the planet. Model testing is so fast in VeriLogger Pro that you can perform true bottom-up testing of every model in your design, a critical step often skipped in the race to market. Test vectors can be imported or exported from HP logic analyzers, pattern generators, and 3rd party VHDL, Verilog, and SPICE simulators for reuse. Simulation features include waveform viewing, optimized gate-level simulation, single-step debugging, point-and-click breakpoints, hierarchical browser for project management, and batch execution.

Windows NT/2000/XP