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hw6_3a_Cin.pdf
hw6_3b_Cint.pdf
hw6_3c_gamma.pdf
HW6#3a Cin of NAND by 1ua test Current
.lib '/home/ff/ee141/MODELS/g25.mod' TT
*****************************************
* Circuit
* vdd
* |
* in---(NAND)--out
* |
*(VIN)
* |
* 0
*****************************************
* Parameter
*****************************************
.param vddp=2.5
*.param cload=0fF
*.param f=1
*****************************************
* Netlist
*****************************************
VDD vdd 0 'vddp'
I 0 in 1u
*C1 out 0 'cload'
.subckt NAND2 Vdd Gnd VinA VinB Vout
*M<name> <drain> <gate> <source> <bulk> <model> <geometry>
Mp1 Vout VinA Vdd Vdd pmos l=0.24u w=0.6u
Mp2 Vout VinB Vdd Vdd pmos l=0.24u w=0.6u
Mn1 Vout VinA vmid Gnd nmos l=0.24u w=0.72u
Mn2 vmid VinB Gnd Gnd nmos l=0.24u w=0.72u
.ends
XNAND1 vdd 0 in vdd out NAND2
*initial conditions
.ic v(in)=0
*****************************************
* Analysis
*****************************************
.meas t1 trig v(in) val=0.0001 cross=1 targ v(in) val='vddp/2' cross=1
.meas t2 trig v(in) val='vddp/2' cross=1 targ v(in) val='vddp' cross=1
.options post=2 nomod
.op
.tran 0.01ns 10ns
.END
******
hw6#3a cin of nand by 1ua test current
****** transient analysis tnom= 25.000 temp= 25.000
******
t1= 3.8613E-09 targ= 3.8615E-09 trig= 1.8139E-13
t2= 2.9862E-09 targ= 6.8477E-09 trig= 3.8615E-09
0 to 1.25V C=1uA/ (0.324V/ns) =3.09fF
1.25V to 2.5V = 1uA/ (0.419V/ns) = 2.39fF
Cavg = (3.09+2.39)/2 = 2.74fF
worst case input capacitance = 8.47fF
HW6#3b Delay with Load Capacitance 0 to 100fF
.lib '/home/ff/ee141/MODELS/g25.mod' TT
*****************************************
* Circuit
* vdd
* |
* in---(NAND)--out
* |
|
*(VIN)
C1
* |
|
* 0
0
*****************************************
* Parameter
*****************************************
.param vddp=2.5
.param cload=0fF
*.param f=1
*****************************************
* Netlist
****************************************
VDD vdd 0 'vddp'
*I 0 in 1u
*params = vlow vhigh delay rise fall pulse_width period
*example VIN IN GND PULSE 0 5 .5n .1n .1n .5n 2n
VIN in 0 dc 0 PULSE (0 'vddp' 1p 1p 10n)
C1 out 0 'cload'
.subckt NAND2 Vdd Gnd VinA VinB Vout
*M<name> <drain> <gate> <source> <bulk> <model> <geometry>
Mp1 Vout VinA Vdd Vdd pmos l=0.24u w=0.6u
Mp2 Vout VinB Vdd Vdd pmos l=0.24u w=0.6u
Mn1 Vout VinA vmid Gnd nmos l=0.24u w=0.72u
Mn2 vmid VinB Gnd Gnd nmos l=0.24u w=0.72u
.ends
XNAND1 vdd 0 in vdd out NAND2
*initial conditions
*.ic v(in)=0
*****************************************
* Analysis
*****************************************
*nomod= no model info from library
*For graphical display,"post" will create a *.sw# (for .sweep analysis) or
*a *.tr# file (for transient analysis)
.options brief post=2 nomod
*.op makes hspice determines DC operating point
.op
.meas t_fall trig v(in) val='vddp/2' cross=1 targ v(out) val='vddp/2' cross=1
.tran 0.01ns 1ns sweep cload 0f 100f 1f
.END
tp = 0.69Req* (Cint + Cl)
dtp/dCl = 0.69Req
tp / (dtp/dCl) = Cint + Cl
Cint = 2.71e-10 / 5e3
- 4.94e-14 = 4.8fF
HW6#3c Find Gamma with NAND chain
.lib '/home/ff/ee141/MODELS/g25.mod' TT
*****************************************
* Circuit
* vdd
* |
* in---(NANDx8)--out
* | |
*(VIN) C9
* | |
* 0 0
*****************************************
* Parameter
*****************************************
.param vddp=2.5
*.param cload=0fF
.param fanout=1
.param cin=2.74fF
*****************************************
* Netlist
****************************************
VDD vdd 0 'vddp'
*I 0 in 1u
*params = vlow vhigh delay rise fall pulse_width period
*example VIN IN GND PULSE 0 5 .5n .1n .1n .5n 2n
VIN in 0 dc 0 PULSE (0 'vddp' 1p 1p 10n)
*C1 out 0 'cload'
.subckt NAND2 Vdd Gnd VinA VinB Vout
*M<name> <drain> <gate> <source> <bulk> <model> <geometry>
Mp1 Vout VinA Vdd Vdd pmos l=0.24u w=0.6u
Mp2 Vout VinB Vdd Vdd pmos l=0.24u w=0.6u
Mn1 Vout VinA vmid Gnd nmos l=0.24u w=0.72u
Mn2 vmid VinB Gnd Gnd nmos l=0.24u w=0.72u
.ends
XNAND1 vdd 0 in vdd 1 NAND2
XNAND2 vdd 0 1 vdd 2 NAND2 M='fanout'
XNAND3 vdd 0 2 vdd 3 NAND2 M='fanout**2'
XNAND4 vdd 0 3 vdd 4 NAND2 M='fanout**3
XNAND5 vdd 0 4 vdd 5 NAND2 M='fanout**4'
XNAND6 vdd 0 5 vdd 6 NAND2 M='fanout**5'
XNAND7 vdd 0 6 vdd 7 NAND2 M='fanout**6'
XNAND8 vdd 0 7 vdd out NAND2 M='fanout**7'
C9 out 0 'cin*fanout**8'
*initial conditions
*.ic v(in)=0
*****************************************
* Analysis
*****************************************
*nomod= no model info from library
*For graphical display,"post" will create a *.sw# (for .sweep analysis) or
*a *.tr# file (for transient analysis)
.options brief post=2 nomod
*.op makes hspice determines DC operating point
.op
.meas delay2 trig v(4) val='vddp/2' cross=1 targ v(6) val='vddp/2' cross=1
.meas tran tp param='delay2/2'
.tran 0.01ns 'fanout*1ns' sweep fanout 0.5 5 0.5
.END
Rather than measuring the delay through a single inverter,
measure across a consecutive pair of inverters, and take half of that delay.
This will average out the differences between rising and falling edges, and also
make the measurement independent of the switch level you use to trigger the
delay measurement.
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